The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
As size of IC continues to shrink and with increased density features in an IC, more interconnects are required to connect the features in various levels. Different feature density and feature sizes across the IC render various topographies on the surface of the IC. The variation of topography in the dielectric layer and interconnection, for example, may affect the processing window, compromising the reliability of the IC.
From the foregoing discussion, it is desirable to provide a planarized topography for dielectric and interconnect to increase the reliability of IC.